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SIP12202
New Product
Vishay Siliconix
Synchronous Step Down Controller
DESCRIPTION SIP12202 is a synchronous step down controller designed for use in dc-dc converter circuits requiring output currents as high as 10 amperes. SIP12202 is designed to require a minimum number of external components, simplifying design and layout. It accepts input voltages from 2.7 V to 5.5 V, providing an adjustable output with voltage ranging from 0.6 V to 5.5 V. SIP12202 includes a combination Compensation/ Shutdown pin. Protection features include undervoltage lockout, Power Good output, output current limit, and thermal shutdown. SIP12202 is available in a lead (Pb)-free MLP-33-10 package and is specified to operate over the range of - 40 C to 85 C.
FEATURES * 2.7 V to 5.5 V Input Voltage Range * Adjustable Output Voltage - 0.6 to 5.5 V * For Converter loads up to 10 A * High efficiency - 93% * Uses High Side P-Channel MOSFET * Uses Low Side N-Channel MOSFET * 500 kHz operation * Internal Soft Start * Power Good Indication * Shutdown Pin * Output Current Limit * Minimum External Components * MLP33-10 Package APPLICATIONS * * * * * Distributed Power Desktop & Notebook Computers Battery Operated Equipment Point of Load Regulation DSP Cores
TYPICAL APPLICATION CIRCUIT
VIN VIN VIN DH LX Power Good Compensation/ Shutdown PG DL COMP/SD VOUT
FB AGND P AGNDPGND GND GND
Document Number: 73542 S-52083-Rev. A, 10-Oct-05
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SIP12202
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter VIN, LX to GND FB, PG, Comp/SD to GND Power Dissipationa, b Maximum Junction Temperature Storage Temperature Notes a. Device mounted with all leads soldered or welded to PC board b. Derate 14 mW/C above + 85 C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. Limit 6 - 0.3 to 6 560 125 - 55 to + 150 Unit V mW C
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RECOMMENDED OPERATING RANGE
Parameter Input Voltage Range Output Voltage Adjustment Range Operating Temperature Range Limit 2.7 to 5.5 0.6 to 5.5 - 40 to + 85 Unit V C
SPECIFICATIONS
Parameter Controller Input Voltage Quiescent Current Switching Oscillator Frequency Oscillator Ramp Amplitude Feedback Voltage FB input Bias Current Transconductance Soft Start Inputs and Outputs SD Input Voltage Shutdown Current MOSFET Drivers Break-before-make-time Highside Driver Output Voltage On resistance Rise time - PFET Turn On Fall time - PFET Turn Off Lowside Driver Output Voltage On resistance Rise time - NFET Turn On Fall time - NFET Turn Off VDL RDSLH RDSLL trL tfL VIN = 4.5 V VIN = 4.5 V VIN = 5 V, CL = 2.7 nF VIN = 5 V, CL = 2.7 nF 4.5 5.5 0.85 83 6.6 8.2 1.4 V ns VDH RDSHH RDSHL trH tfH VIN = 4.5 V VIN = 4.5 V VIN = 5 V, CL = 2.7 nF VIN = 5 V, CL = 2.7 nF 4.5 1.3 2.8 64 8 1.9 4.4 V ns tBBM 30 ns VIL IIL 30 0.15 60 V A fOSC VOSC VFB IFB GM 2 4 TA = 25 C 0.591 0.585 VIN Non Switching 400 2.7 0.6 500 1 0.600 0.609 0.615 100 5.5 1 600 V mA kHz V V nA mA/V ms Symbol Test Condition Unless Specified VIN = 5.0 Limits -40 to 85C Mina Typb Maxa Unit
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Document Number: 73542 S-52083-Rev. A, 10-Oct-05
SIP12202
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SPECIFICATIONS
Parameter Protection Under voltage lockout UVLO-Hysteresis Power Good PG Output Voltage PG Leakage Current PG Voltage Threshold PG Threshold Hysteresis Over Current Limit Thermal Shutdown Temperature Thermal Hysteresis MOSFET On Voltage Sense Threshold VDL With respect to VIN -335 Rising 165 20 -300 -265 C C mV VPGOL IPGOL VETH VEH ISINK = 0.5 mA 70 5 0.4 1 V A %VOUT %VOUT VUVLO Rising 2.3 2.4 0.10 2.5 V Symbol Test Condition Unless Specified VIN = 5.0 Limits -40 to 85C Mina Typb Maxa Unit
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NOTES: a) The algebriac convention whereby the most negative value is a minimum and the most positive a maximum. b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
PIN CONFIGURATION
PIN DESCRIPTION
Part Number 1 2 3 4 5, 10 6 7 8 9 Name COMP/SD FB AGND PG VIN DL PGND LX DH Feedback input Analog Ground Indicates that the output voltage is in regulation Input voltage for the power MOSFETs and their gate drive Lowside gate drive Power Ground Connection for the inductor node Highside gate drive Function Combination Compensation and Shut down pin
ORDERING INFORMATION
Part Number SIP12202DM-T1-E3 Eva Kit SIP12202DB Temperature Range -40 to 85 C Temperature Range -40 to 85 C Package MLP33-10 Board Surface Mount
Document Number: 73542 S-52083-Rev. A, 10-Oct-05
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SIP12202
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
SIP12202
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0.45 V
PG
FB Vin
Vin
UVLO
Over Temp
Over Voltage
DH
Soft Start
Shut Down Over Current Sense
Comp LX
FB
GM PWM Comp 0.6 V OSC 500KHz Vosc
Gate Control Logic BBM Vin
DL
Pgnd
SD/Comp
Agnd
DETAILED OPERATIONAL DESCRIPTION Enable/ON State: The COMP/SD pin has 10 A pull up current to ensure auto startup as soon as the pin is released by the external pull down MOS. When the internal reference is ready, there will be a clamp current applied at COMPSD; this is to ensure the COMPSD pin will not go below 600 mV inadvertently due to the amplifier excursion or noise. The COMPSD has to go above 600 mV to enable the chip fully. Disable/Shutdown/Off State To disable the chip, the COMP/SD pin has to pulled below 150 mV typically and the external pull down MOSFET has to be able to sink at least 250 A. Once the pin reaches a voltage below the 150 mV level, the chip will go into shutdown mode with only essential curcuitry alive and the current bias of the chip will be cut down to 30 A level typically. Both High Side and Low Side Gates are off. UVLO: The chip enters into Under Voltage Lockout when VIN is below 2.3 V (typical). Both High Side Gate and Low Side Gate will be turned off. The chip will go out of UVLO mode when VIN is above 2.4 V (typical).
Soft Start: Once the chip is out of shutdown and UVLO mode the soft start is initiated. The soft start is done accomplished by ramping up the internal reference. During soft start mode the chip can not enter into fault mode. If there is an over current condition (current limit condition), the High Side Gate will be turned off and the Low Side will be turned on. Once the soft start timing elapses, the chip enters into a normal state of operation. Output Over Voltage State: When the Output voltage goes above 1.083 times nominal Output Voltage, the High Side Gate will be turned off and the Low Side Gate will be on. The condition will persist until the Output voltage drops below the trigger voltage minus a hysteresis. Output Over Current State: The SIP12202 will enter a cycle by cycle over current condition when the voltage on the LX pin falls below VIN by 300 mV. During the over current condition the High Side MOSFET is turned off for the duration of the existing cycle. At the beginning of the next cycle the High Side MOSFET turns on and the LX voltage is measured again. If the over current condition still exists, the High Side MOSFET is turned off again. This is repeated seven consecutive times after which the IC will go into a fault state. If the over current condition is removed before seven consecutive cycles the IC reverts to normal operating mode.
Document Number: 73542 S-52083-Rev. A, 10-Oct-05
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SIP12202
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Fault State: The IC can only enter into Fault mode after the soft start mode has ended and seven consecutive over current condition cycles has occurred. Once it enters the Fault state, with the High Side MOSFET turned off and the Low Side MOSFET turned on, any occurring over current condition will be ignored. The Fault State will last for seven soft start cycles. After which the IC will enter Soft Start mode. If the over current condition is removed the IC will operate normally, otherwise the over current sequence is repeated. This fault scheme minimizes thermal stress on the external power MOSFET switches Over Temperature: When the temperature of the chip goes above 165 C, the chip enters into over temperature shutdown. The High Side gate will be off and the Low Side gate will be on. Only system monitor circuitry will be active. Once the temperature of the chip drops below 145 C, the chip enters into the normal operation mode. Power Good: Power Good State: When the output is above 0.75 times nominal output voltage, the PC signal will be high to indicate that the output voltage is available for external use. The PG pin requires a pull up resistor. Setting the Output Voltage: An output voltage between 0.8 V and (0.9 V x VIN) 0.6 V and VIN and can be configured by connecting FB pin to a resistive divider between the output and GND. Select resistor R2 in the 1 k to 10 k range. R1 is then given by:
R1 = R2
FREQUENCY (kHz)
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TYPICAL CHARACTERISTICS
100 95 90 Vout = 3.3 V
EFFICIENCY (%)
85 80 75 70 65 60 55
Vout = 2.5 V
Vin = 5.0 V 50 0 2 4 6 8 10
LOAD CURRENT (A) EFFICIENCY vs LOAD CURRENT
600
550
Vin = 5.0 V 500
450
Vin = 2.7 V
400 -45
-10
25
60
95
130
TEMPERATURE (C) OSCILLATOR FREQUENCY Vs TEMPERATURE
0.615
(V V
OUT FB
-1
)
VOLTAGE ( V)
0.605 Vin = 2.7 V to 5.0 V
where VFB = 0.6 V.
VOUT
0.595
R1 FB R2
0.585 -45 -10 25 60 95 130
TEMPERATURE (C) FEEDBACK THRESHOLD Vs TEMPERATURE
0.6 V
Document Number: 73542 S-52083-Rev. A, 10-Oct-05
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SIP12202
Vishay Siliconix
TYPICAL CHARACTERISTICS
-260
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2.5
-280
2.45
Vin = 2.7 V
VOLTAGE ( mV)
VOLTAGE ( V)
130
-300 Vin = 5.0 V
2.4
-320
2.35
-340 -45
2.3
-10 25 60 95
-45
-10
25
60
95
130
TEMPERATURE (C) CURRENT SENSE VOLTAGE Vs TEMPERATURE
0.8
10
TEMPERATURE (C) UVLO Vs TEMPERATURE
5
CURRENT (mA)
CURRENT (nA)
Vin = 5.0 V 0.6
Vin = 2.7 V 0 Vin = 5.0 V -5
Vin = 2.7 V
0.4 -45
-10
-10
25
60
95
130
-45
-10
25
60
95
130
TEMPERATURE (C) QUIESCENT CURRENT Vs TEMPERATURE
50
TEMPERATURE (C) FB INPUT BIAS CURRENT Vs TEMPERATURE
80
30
Vin = 5.0 V
VOLTAGE (% VOUT)
40
CURRENT (mA)
75
Vin = 5.0 V
Vin = 2.7 V
20 Vin = 2.7 V 10 -45 -10 25 60 95 130
70 -45 -10 25 60 95 130
TEMPERATURE (C) SHUTDOWN CURRENT Vs TEMPERATURE
TEMPERATURE (C) POWER GOOD THRESHOLD Vs TEMPERATURE
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Document Number: 73542 S-52083-Rev. A, 10-Oct-05
SIP12202
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TYPICAL WAVEFORMS
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VLX = 5 V/div
VOUT = 500 mV/div
DH = 5 V/div
DL = 5 V/div Inductor Current 5 A/div
Inductor Current 5 A/div
1 s/div VIN = 5 V, VOUT = 2.5 V, Load Current = 5 A, L = 1.5 H, COUT = 220 uF X 2 Typical Switching Waveform
10 s/div VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A to 8 A Step, L = 1.5 H, COUT = 220 uF X 2 Load Transient Response
Comp/SD = 1 V/div VOUT = 1 V/div
PG = 5 V/div
VOUT = 20 mV/div
Inductor Current 5 A/div
1 ms/div VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A, Output Filter Cap = 220 uF X 2 Soft Start
1 s/div VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A, L = 1.5 H, COUT = 220 uF X 2 Output Voltage Ripple
Comp/SD = 1 V/div
VOUT = 1 V/div
Inductor Current 5 A/div
1 ms/div VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A, Output Filter Cap = 220 uF X 2 Shut Down
Document Number: 73542 S-52083-Rev. A, 10-Oct-05
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SIP12202
Vishay Semiconductors
New Product
Input Capacitor Selection: To minimize current pulse induced ripple caused by the step-down controller and interference of large voltage spikes from other circuits, a low-ESR input capacitor is required to filter the input voltage. The input capacitor should be rated for the maximum RMS input current: APPLICATION NOTES Inductor Selection: An inductor is one of the energy storage component in a converter. Choosing an inductor means specifying its size, structure, material, inductance, saturation level, dc-resistance (DR.), and core loss. Fortunately, there are many inductor vendors that offer wide selections with ample specifications and test data, such as Vishay Dale. The following are some key parameters that users should focus on. In PWM mode, inductance has a direct impact on the ripple current. The peak-to-peak inductor ripple current can be calculated as
IP - = VOUT (VIN - V OUT) VIN Lf
I RMS = I LOAD(m ax)
V OUT V OUT 1 - V IN V IN
It is common practice to rate for the worst-case RMS ripple that occurs when the duty cycle is at 50%:
I RMS =
P
I LOAD(max) 2
where f = switching frequency. Higher inductance means lower ripple current, lower current, lower voltage ripple on both input and output, and higher efficiency, unless the resistive loss of the inductor dominates the overall conduction loss. However, higher inductance also means a bigger inductor size and a slower response to transients. In PSM mode, inductance affects inductor peak current, and consequently impacts the load capability and switching frequency. For fixed line and load conditions, higher inductance results in a lower peak current for each pulse, a lower load capability, and a higher switching frequency. The saturation level is another important parameter in choosing inductors. Note that the saturation levels specified in data sheets are maximum currents. For a dc-todc converter operating in PWM mode, it is the maximum peak inductor current that is relevant, and which can be calculated using these equations:
I PK = I OUT + IP - 2
P
Output Capacitor Selection: The selection of the output capacitor is primarily determined by the ESR required to minimize voltage ripple and current ripple. The desired output ripple VOUT can be calculated by:
1 VOUT = (I m ax- I m in) ESR + 8fCOUT
Current ripple can be calculated by:
(I m ax- I m in) = T V OUT ( V IN - V OUT)
L V IN
Where: VOUT = Desired Output Ripple Voltage f = switching frequency Imax = Maximum Inductor Current Imin = Minimum Inductor Current T = Switching Period Multiple capacitors placed in parallel may be needed to meet the ESR requirements. However if the ESR is too low it can cause instability. MOSFET Selection: The key selection criteria for the MOSFETs include maximum specifications for on-resistance, drain-source voltage, gate source, current, and total gate charge Qg. While the voltage ratings are fairly straightforward, it is important to carefully balance on-resistance and gate charge. In typical MOSFETs, the lower the on-resistance, the higher the gate charge. The power loss of a MOSFET consists of conduction, gate charge, and crossover losses. For lower-current application, gate charge losses become a significant factor, so low gate charge MOSFETs, such as Vishay Siliconix's LITTLE FOOT family of PWM-optimized devices, are desirable.
This peak current varies with inductance tolerance and other errors, and the rated saturation level varies over temperature. So a sufficient design margin is required when choosing current ratings. A high-frequency core material, such as ferrite, should be chosen, the core loss could lead to serious efficiency penalties. The DCR should be kept as low as possible to reduce conduction losses.
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Document Number: 73542 S-52083-Rev. A, 10-Oct-05
SIP12202
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Compensation:
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VIN VOUT
R1 FB GM R2 R3 0.6 V C1 ESR OSC 500KHz Vosc PWM Comp C2 COUT Compensation L VOUT
The SiP12201 uses voltage mode control in conjunction with a high frequency Transconductance error amplifier. The voltage feedback loop is compensated at the Comp/ SD pin, which is the output node of the error amplifier. The feedback loop is generally compensated with an RC + C (one pole, one zero) network from comp to GND. Loop stability is affected by the values of the inductor, the output capacitor, the output capacitor ESR, and the error amplifier compensation network. The ideal Bode plot for a compensated system would be gain that rolls off at a slope of -20 dB/decade, crossing 0dB at the desired bandwidth and a phase margin greater than 90 for all frequencies below the 0dB crossing. The compensation network used with the error amplifier must provide enough phase margin at the 0dB crossover frequency for the overall open-loop transfer function to be stable. The following guidelines will calculate the compensation pole and zero to stabilize the SiP12201. The inductor and output capacitor values are usually determined by efficiency, voltage and current ripple requirements. The inductor and the output capacitor create a double pole at the frequency and a -180 phase change:
The fZ(ESR) typically should be higher than the fp(LC) and give a 90 phase boost. R3 and C1 will establish the second zero of the system. The frequency of the zero should be 2X lower than the double pole frequency of the inductor and the output capacitor.
fZ(comp) =
1 2 R3C1
Choose a value for R3 usually between 1 k and 10 k. This second zero will provide the second 90 phase boost and will stabilize the closed loop system. The second pole should be placed at 1/2 the switching frequency.
C2 =
C1 2 R1 C1 FSW-1
f p(LC) =
1 2 L * COUT
The ESR of the output capacitor and the output capacitor value form a zero at the frequency:
f Z(ESR) =
1 2 (ESR)(C OUT)
Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting at the load a variable frequency small signal voltage between the output and the feedback network and using an RC network box to iterate toward the final values; or by obtaining the optimum loop response using a network analyzer to measure the loop Gain and Phase. Layout: As in the design of any switching dc-to-dc converter, driver careful layout will ensure that there is a successful transition from design to production. One of the few drawbacks of switching dc-to-dc converters is the noise induced by their high-frequency switching. Parasitic inductance and capacitance may become significant when a converter is switching at 500 kHz. However,
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Document Number: 73542 S-52083-Rev. A, 10-Oct-05
SIP12202
Vishay Semiconductors
New Product
noise levels can be minimized by properly laying out the components. Here are some general guidelines for laying out a step-down converter with the SIP12202. Since power traces in step down converters carry pulsating current, energy stored in trace inductance during the pulse can cause high-frequency ringing with input and output capacitors. Minimizing the length of the power traces will minimize the parasitic inductance in the trace. The same pulsating currents can cause voltage drops due to the trace resistance and cause effects such as ground bounce. Increasing the width of the power trace, which in-creases the cross sectional area, will minimize the trace resistance. In all dc-to-dc converters the decoupling capacitors should be placed as close as possible to the pins being decoupled to reduce the noise. The connections to both terminals should be as short as possible with low-inductance (wide) traces. In the SIP12202 converters, the VIN is decoupled to PGND. It may be necessary to decouple VDD to AGND, with the decoupling capacitor being placed adjacent to the pins. AGND and PGND traces should be isolated from each other and only connected at a single node such as a "star ground".
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Document Number: 73542 S-52083-Rev. A, 10-Oct-05

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